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This file describes the new features in the Xilinx™ Integrated Software Environment (ISE) 5.2i software release. It contains the following sections:
The following members of the Spartan™-IIE family are now available in ISE 5.2i:
These devices are available in the ISE-BaseX, ISE-Alliance, and ISE-Foundation configurations.
Following are the top new features in this release, presented in the order of the ISE 5.2i software design flow. For detailed information, see the "ISE 5.2i Documentation" chapter of the ISE 5.2i Release Notes and Installation Guide available from the support.xilinx.com Software Manuals collection.
Design Entry
New NGC and NGO Design Flow in Project Navigator
The Project Navigator Graphical User Interface (GUI) includes a new flow in which it accepts NGC or NGO files as top-level source files.
PACE Enhancements
The Pinout Area Constraints Editor (PACE) GUI now includes real-time, interactive checking of I/O assignments based on the Design Rule Check (DRC) rules.
Synthesis
XST Enhancements
Xilinx Synthesis Technology (XST) includes the following enhancements:
- Support for additional Verilog 2001 constructs as follows:
- Multi-dimensional arrays
- Power operators
- Re-entrant tasks and recursive functions
- Propagation of initial signal values (for flip-flops only)
- Macro inference improvements as follows:
- Pipelining of Look-Up Table (LUT) multipliers
- BlockROM inference
Verification
HDL Simulation Libraries Enhancements
Functional and timing simulation now runs two to three times faster when using the BlockRAM Verilog models. In addition, the netlist writer now optimizes buffer insertion, which results in fewer buffers in the timing simulation netlist. This makes compiling and simulating the netlist slightly faster and makes debugging easier.
RTL Viewer Enhancements
The Register Transfer Level (RTL) Viewer GUI now displays designs processed by XST using the Incremental Synthesis option. In addition, the display of state machine symbols includes more information available through tooltips. The display of XOR symbols now includes individual pins when there are eight input pins or less.
ChipScope Pro Core Inserter Integration with Project Navigator
Using the 5.2i ChipScope™ Pro software, you can now run the ChipScope Pro core inserter from the Project Navigator GUI.
ModelSim Xilinx Edition II Support
ModelSim™ Xilinx Edition II is upgraded to version 5.6e.
Implementation
Timing Report Enhancements
The I/O Datasheet Report now includes clock phase, which reports more accurate input setup and hold times and clock to out times. This report is available from the Timing Analyzer GUI or the TRACE command line tool.
Device Configuration
iMPACT Enhancements
The iMPACT GUI is now integrated with the Data2BRAM command line tool and allows you to directly download ELF files into a Virtex-II Pro™ device. For Virtex-II Pro devices with multiple processors, you can associate ELF files with individual processors. You can also now use iMPACT to create System ACE™ CompactFlash (CF) files containing ELF files.
Following are new features in partner releases related to the Xilinx ISE 5.2i software release.
RTL Analysis
LEDA
The Xilinx ruleset version 4.0 for LEDA version 3.3 includes over 100 rules specifically targeted for Virtex™-II and Virtex-II Pro devices. For example, the rules can detect large CASE statements and nested IF statements that may create timing delays for high performance designs. In addition, the LEDA software provides comprehensive feedback on how to optimize your RTL file for improving quality of results (QoR) and reuse.
Synthesis
Synplicity
The Synplicity® Synplify® and Synplify Pro® synthesis software and Amplify® Physical Optimizer™ physical synthesis software support the latest Xilinx device families.
Mentor
The Mentor® LeonardoSpectrum™ synthesis software supports the latest Xilinx device families.
Formal Verification and Equivalency Checking
Synopsys
The Synopsys® Formality® software supports the latest Xilinx device families. The Formality software also runs faster, because the Formality software now only loads the UNISIM or SIMPRIM models for the components in the design.
Verplex
The Verplex™ Conformal™ Logic Equivalence Checker (LEC) software supports the latest Xilinx device families.
Static Timing Analysis
Synopsys
The Synopsys PrimeTime® software includes the following enhancements:
- The new simprims.db library addresses missing timing arcs related to Multi-Gigabit Transceivers (MGTs).
As a result of this new library, PrimeTime now produces more accurate timing results for paths related to MGTs and no longer has problems when back-annotating Standard Delay Format (SDF) file information for MGTs.
- The PrimeTime software supports the latest Xilinx device families.
When targeting Xilinx devices, you can now use PrimeTime to analyze the timing of the post-PAR netlist and to achieve timing closure.
Co-Design
CoWare
CoWare™ supports a SystemC™-based modeling platform for IBM® PowerPC® 405 and CoreConnect™ designs. This allows you to quickly assemble a virtual prototype of a Virtex-II Pro-based embedded system. CoWare software then allows you to functionally validate your design, analyze performance, and explore hardware and software tradeoff issues at an early stage in your design process.
Celoxica
The Celoxica™ DK1.1 design suite, which includes Platform Abstraction Layer (PAL) and Data Streaming Manager (DSM) technologies, now supports a co-design methodology for Xilinx Virtex-II Pro devices. This helps you co-develop and co-verify the hardware and software parts of the design from a single design environment.
Co-Verification
Mentor
The Mentor Seamless-CVE™ tool now supports a fully integrated co-verification solution for Xilinx Virtex-II Pro devices. The solution features a cycle-accurate Instruction Set Simulator (ISS) for IBM PowerPC 405, support for a Xilinx-specific On-Chip Memory (OCM) controller, and support for design examples included in the Virtex-II Pro Developer's Kit.
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Software Updates
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Software Manuals
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Note For the ISE 5.2i software release, the Libraries Guide and Constraints Guide installed with your software include updated information about the latest Xilinx device families. In addition, the Libraries Guide and Constraints Guide on the Web are updated periodically with the latest device-specific information. Check the Software Manuals website for the most up-to-date information.
Tech Tips
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Forums
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Problem Solvers
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WebCase
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